1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a new structure for dual-chip integrated circuit package which is characterized in the use of leads of a leadframe to provide firm support and electrical connection with external devices to the chips.
2. Description of Related Art
Integrated circuit chips are typically packed in packages for easy handling and utilization. To allow increased functionality from a single integrated circuit package, it is usually desired to pack two or more integrated circuit chips rather than just one in the integrated circuit package. An integrated circuit package that packs two integrated circuit chips therein is customarily referred to as a dual-chip integrated circuit package.
The U.S. Pat. No. 5,793,108 discloses a dual-chip integrated circuit package. FIG. 5 is a schematic sectional diagram showing the structure of this dual-chip integrated circuit package. As shown, this dual-chip integrated circuit package includes a leadframe 200 having a die pad 201 for mounting a first integrated circuit chip 220 and a second integrated circuit chip 240. The first integrated circuit chip 220 has its front side 221 attached to the die pad 201 by means of an insulative adhesive film 210. The bonding pads 223 on the first integrated circuit chip 220 are electrically connected via a plurality of gold wires 250 to the first surface 202a of the leads 202 of the leadframe 200. An insulative adhesive layer 230 is then coated on the back side 222 of the first integrated circuit chip 220 for attaching the first integrated circuit chip 220 to the back side 242 of the second integrated circuit chip 240. The bonding pads 243 on the front side 241 of the second integrated circuit chip 240 are electrically connected via a plurality of gold wires 260 to a second surface 202b of the leads 202. Further, an encapsulant 270 is formed to encapsulate the first integrated circuit chip 220, the second integrated circuit chip 240, and the inner part of the leads 202. Electronic components and electric circuits are formed on the front side 221 of the first integrated circuit chip 220 and the front side 241 of the second integrated circuit chip 240.
The forgoing dual-chip integrated circuit package, however, has the following drawbacks. First, it requires the bonding pads 223 on the front side 221 of the first integrated circuit chip 220 to be exposed out of the die pad 201 so as to facilitate the connection of the gold wires 250. This requires the jointed area between the first integrated circuit chip 220 and the die pad 201 to be smaller than the area of the front side 221 of the first integrated circuit chip 220. However, after the second integrated circuit chip 240 has been attached to the first integrated circuit chip 220, the beneath of the bonding pads 243 on the second integrated circuit chip 240 is a void space. As a consequence, as shown in FIG. 6, during the wire-bonding process to connect the bonding wires 260, the second integrated circuit chip 240 is only partly supported by the fixture 280, which would easily cause the areas near the bonding pads 243 on the second integrated circuit chip 240 and the bonding pads 223 on the first integrated circuit chip 220 to be cracked. Second, since the front side 221 of the first integrated circuit chip 220 is attached to the die pad 201 in a direct face-to-face manner, the first integrated circuit chip 220 could be easily subject to delamination during temperature changes in the manufacture process. This is because that the first integrated circuit chip 220 differs in Coefficient of Thermal Expansion (CTE) from the die pad 201. The direct face-to-face attachment also requires the insulative adhesive film 210 to be large enough to cover the whole of the die pad 201. This practice, however, would considerably increase the manufacture cost. Moreover, the insulative adhesive film 210 being made large would hamper the drainage of the air between the insulative adhesive film 210 and the die pad 201 and the air between the insulative adhesive film 210 and the first integrated circuit chip 220, which would undesirably cause voids to be formed therebetween. Under high-temperature condition, the existence of such voids would cause a popcorn effect, which could damage the integrated circuit package structure. Still one drawback is that when the foregoing dual-chip integrated circuit package is formed as a low profile package, the gap between the bottom side of the die pad and the bottom of a cavity of an encapsulation mold (not shown) would become very small, causing the resin flow introduced into the encapsulation mold to be slowed down when passing through the gap, resulting in the undesired thus-forming of voids in the formed encapsulant. The forming of these voids could also lead to the problem of a popcorn effect.